VeriGen
One of the first LLMs for Verilog: CodeGen fine-tuned on GitHub Verilog and textbooks, beating GPT-3.5 on RTL tasks.
About
VeriGen is an early LLM for hardware design from Shailja Thakur's group at NYU, and one of the first serious attempts to generate Verilog RTL with language models. The team fine-tuned Salesforce's CodeGen models (2B, 6B, and 16B) on Verilog scraped from GitHub plus content from Verilog textbooks, then evaluated functional correctness with a custom test suite and testbenches they designed for the purpose.
The headline result from the paper: the fine-tuned 16B model beat GPT-3.5-turbo by 1.1% overall on their problem set, and showed a 41% improvement in generating syntactically correct Verilog versus its pre-trained base. It is a completion-style model rather than an instruction-tuned assistant, so you prompt it with a partial module header rather than a chat command. The training code is Apache 2.0 and the weights are open, though the project has seen little maintenance since 2024.
Specs
Context window
Pricing
Free quota
API access
Weights
Released
Benchmarks
- Custom Verilog problem suite: fine-tuned 16B beats GPT-3.5-turbo by 1.1% overall (provider-reported, arXiv:2308.00708)
- 41% improvement in syntactically correct Verilog vs pre-trained base (provider-reported)
Provider-reported unless a source says otherwise. Benchmarks are marketing-adjacent by nature — treat them as directional.
Use cases
Trust score — 6/10
Scored 6/10 (metrics tier, metrics-v1). Evidence: published paper (arXiv:2308.00708) with a real functional-correctness evaluation rather than vibe checks; weights and Apache-2.0 training code public. Strengths: pioneering Verilog LLM, genuinely open artifacts. Docked for: (1) evaluation is on the authors' own small problem set, not an established benchmark; (2) completion-style model with no instruction tuning; (3) no maintenance since 2024 and superseded by RTLCoder-class models.
How the trust score is built
Full methodology →- Adoption · stars/downloads, log-scaled vs peers
- 6.0/10
- Maintenance · recency, releases, issue load
- 4.0/10
- Openness · license + docs
- 9.0/10
- Manual review · sanity read + red-flag check
- 6.0/10
- · Pioneering Verilog LLM with functional-correctness eval
- · Author's own small problem set; completion-style model; unmaintained since 2024