RTLCoder

RTLCoder is an open-source Verilog RTL generation project from HKUST that set a new bar for non-commercial hardware design models. Its core contribution is an automated flow that generates a large labeled dataset of Verilog design problems and answers, addressing the severe data shortage for chip-design tasks, plus a training scheme driven by code-quality feedback that pushes the model past plain fine-tuning. The team released four models, including RTLCoder-Deepseek-v1.1 (a DeepSeek-Coder-6.7B fine-tune, the strongest) and RTLCoder-v1.1 (Mistral-based), along with GPTQ and GGUF quantized builds.

The authors claim the quality-feedback training lifts the models above GPT-3.5 on the VerilogEval and RTLLM benchmarks. Everything is open: the data generation flow, the training data, the training code, and the models. For hardware teams that need RTL generation without sending proprietary designs to a commercial API, it is the most practical open option in its class.

• VerilogEval and RTLLM: best variant (RTLCoder-Deepseek-v1.1) claimed to outperform GPT-3.5 (provider-reported, repo)
• Independent RTL-Repo eval includes RTLCoder alongside GPT-4, Starcoder2, and VeriGen