Astrus
AI that automates analog chip layout, the most stubbornly manual step in semiconductor design.
About
Astrus is a Toronto and Waterloo startup applying reinforcement learning to analog and mixed-signal chip layout. Analog layout is still done largely by hand: engineers place transistors one at a time while accounting for physical effects that digital abstractions ignore, and a single chip can take weeks of back-and-forth between layout and simulation. Astrus says its system learns in a physics-aware simulation environment and generates thousands of manufacturable candidate layouts, with high-speed interconnect (SERDES) circuits as the first focus.
The company was founded by Brad Moon and Zeyi Wang with RL researcher Kenny Young, and has raised an $8 million round led by Khosla Ventures (2025) plus a $12 million Series A led by Caffeinated Capital (September 2026), with an October 2026 product launch planned. The honest position is that this is still pre-launch: no named customers, no revenue, and no independently audited benchmarks have been disclosed. The speed claims (layouts in seconds instead of months) are company projections, but investor interest is real and the data-scarcity problem it addresses is genuine.
What it can do
- Physics-aware reinforcement learning for analog layout generation
- Thousands of candidate layouts produced in a manufacturing-rules simulation
- Initial focus on SERDES high-speed interconnect circuits
- Synthetic training data generated in-simulation (sidesteps the closed physical-design data problem)
- Engineer-in-the-loop workflow: AI proposes, humans verify
- Inspired by AlphaGo-style search applied to transistor placement and routing
Setup
- Follow Astrus at astrus.ai for the October 2026 product launch; access is currently by engagement, not self-serve.
- Share your analog or mixed-signal design targets (the team is focused on high-speed interconnects).
- Evaluate generated candidate layouts against your own simulation and verification flow.
- Keep human engineering review and signoff in place for manufacturability.
Prerequisites
An analog or mixed-signal chip design program; direct engagement with the Astrus team.
Use cases
Works with
Trust score — 6/10
Scored 6/10 (metrics tier, metrics-v1). Evidence: $8M seed (Khosla, 2025) and $12M Series A (Caffeinated, Sept 2026) corroborated by Pulse2, BetaKit-derived reporting, and the live astrus.ai site. Strengths: strong backers, genuinely hard problem, experienced RL team. Docked for: (1) product not yet launched, zero named customers or benchmarks; (2) layout quality and time-saving claims are untested company projections. License: proprietary.
How the trust score is built
Full methodology →- Adoption · stars/downloads, log-scaled vs peers
- 5.0/10
- Maintenance · recency, releases, issue load
- 7.0/10
- Openness · license + docs
- 6.0/10
- Manual review · sanity read + red-flag check
- 7.0/10
- · $8M seed led by Khosla Ventures (2025, Pulse2) + $12M Series A led by Caffeinated Capital (Sept 2026, BetaKit-derived reporting)
- · astrus.ai verified live, states October 2026 product launch; focus on SERDES high-speed interconnects
- · Founders Brad Moon, Zeyi Wang; RL researcher Kenny Young
- · No named customers, no revenue, no independent benchmarks disclosed; layout speed claims are projections
Sources
Every fact above was checked against these sources. Where a claim comes from the provider and couldn't be independently verified, the text says so.